pyverilator
Python wrapper for verilator model (by csail-csg)
qemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms. (by Xilinx)
| pyverilator | qemu | |
|---|---|---|
| 1 | 1 | |
| 70 | 225 | |
| - | 1.8% | |
| 0.0 | 4.0 | |
| 3 months ago | 6 days ago | |
| Python | C | |
| MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
pyverilator
Posts with mentions or reviews of pyverilator.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-01.
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How to compare HDL simulation/implementation results to Matlab?
I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.
qemu
Posts with mentions or reviews of qemu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-01.
-
How to compare HDL simulation/implementation results to Matlab?
I'd probably simulate both the accelerator and the AXI wrapper. One could instantiate a risc-v core to drive the AXI bus under simulation. gem5 or qemu see the Xilinx fork with AXI support.
What are some alternatives?
When comparing pyverilator and qemu you can also consider the following projects:
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
tpm2-tss - OSS implementation of the TCG TPM2 Software Stack (TSS2)
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
kvm-guest-drivers-windows - Windows paravirtualized drivers for QEMU\KVM
myhdl - The MyHDL development repository
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
keyforge-burger-inserts - Keyforge Deckbox Inserts
SheepDog - Distributed Storage System for QEMU
CastFORM - A Pokemon TCG Deck Registration Sheet generator in Flutter