find_first_set
Find first set operation in Verilog-2001 with logarithmic complexity. (by sifferman)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| find_first_set | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 1 | 1,897 | |
| - | 2.0% | |
| 0.0 | 6.3 | |
| over 2 years ago | 18 days ago | |
| Verilog | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
find_first_set
Posts with mentions or reviews of find_first_set.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-19.
-
How to compute log2 of non-constant logic variable?
I just had this problem. I made this O(logn) implementation: https://github.com/E4tHam/find_first_set
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing find_first_set and darkriscv you can also consider the following projects:
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
find_first_set vs open-fpga-verilog-tutorial
darkriscv vs biriscv
darkriscv vs XiangShan
darkriscv vs riscv
darkriscv vs VexRiscv
darkriscv vs Cores-VeeR-EH1
darkriscv vs friscv
darkriscv vs meta-riscv
darkriscv vs f4pga-examples
darkriscv vs open-fpga-verilog-tutorial
darkriscv vs ice-chips-verilog
darkriscv vs scr1