blarney
darkriscv
| blarney | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 89 | 1,897 | |
| - | 2.0% | |
| 7.1 | 6.3 | |
| 1 day ago | 22 days ago | |
| Haskell | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
blarney
-
Clash: A Functional Hardware Description Language
As described in my other comment, Clash is not like Chisel in that Clash compiles Haskell source code directly, while Chisel is an EDSL (in Scala)
Since you’re more familiar with Haskell, perhaps have a look at Blarney: https://github.com/blarney-lang/blarney/blob/master/Doc/ByEx...
darkriscv
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog