Haskell Verilog

Open-source Haskell projects categorized as Verilog
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Haskell Fpga Systemverilog Hardware Asic
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Top 5 Haskell Verilog Projects

Verilog

  1. clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Project mention: Spade Hardware Description Language | news.ycombinator.com | 2025-05-12

    I thought that this was about the hardware description language Clash developed by some ex-colleagues, but it appeared to be something else. Clash [1] is based on the functional programming language Haskell and it can output to VHDL, Verilog, or SystemVerilog.

    Although the last official release mentioned on the website is from 2021, it is still actively developed on GitHub [2]. See also contranomy [3] for a non-pipelined RV32I RISC-V core written in Clash.

    [1] https://clash-lang.org/

    [2] https://github.com/clash-lang/clash-compiler

    [3] https://github.com/christiaanb/contranomy

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  3. sv2v

    SystemVerilog to Verilog conversion

  4. Reduceron

    FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to

  5. verismith

    Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

  6. blarney

    Haskell library for hardware description

  7. InfluxDB

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Haskell Verilog discussion

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Haskell Verilog related posts

  • Verilog functions and wires

    1 project | /r/Verilog | 11 Jun 2023

  • An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs

    5 projects | /r/ProgrammingLanguages | 3 May 2023

  • A circuit simulator that doesn't look like it was made in 2003

    5 projects | news.ycombinator.com | 14 Dec 2022

  • HDL desugaring

    1 project | /r/FPGA | 12 Aug 2022

  • please tell me I'm not the only twat who's ended up on this page

    3 projects | /r/ProgrammerHumor | 29 Jun 2022
  • A note from our sponsor - InfluxDB
    www.influxdata.com | 1 Sep 2025
    InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now. Learn more →

Index

What are some of the best open-source Verilog projects in Haskell? This list will help you:

# Project Stars
1 clash-ghc 1,530
2 sv2v 660
3 Reduceron 441
4 verismith 111
5 blarney 104

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