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Really out there, but we use verilog to design and test simple genetic circuits: https://github.com/CIDARLAB/cello
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I would check out Chisel, https://www.chisel-lang.org/ . It's a hardware construction language that outputs synthesizable Verilog and leverages a lot of modern programming paradigms. It was developed by Berkeley as they were creating the RISC-V ISA. Like others have said the industry is slow to change but I've seen some adoption of it in commercial and govt. Plus SiFive is doing quite well with it.
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There's Clash, which isn't widely used, but is awesome. That said, I come from a traditional software background and have only had to use HDLs for minor tweaks at work. I wonder how the learning curve would be for Firmware Engineers.
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