please tell me I'm not the only twat who's ended up on this page

This page summarizes the projects mentioned and recommended in the original post on reddit.com/r/ProgrammerHumor

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  • cello

    Genetic circuit design automation (by CIDARLAB)

    Really out there, but we use verilog to design and test simple genetic circuits: https://github.com/CIDARLAB/cello

  • chisel3

    Chisel 3: A Modern Hardware Design Language

    I would check out Chisel, https://www.chisel-lang.org/ . It's a hardware construction language that outputs synthesizable Verilog and leverages a lot of modern programming paradigms. It was developed by Berkeley as they were creating the RISC-V ISA. Like others have said the industry is slow to change but I've seen some adoption of it in commercial and govt. Plus SiFive is doing quite well with it.

  • SonarQube

    Static code analysis for 29 languages.. Your projects are multi-language. So is SonarQube analysis. Find Bugs, Vulnerabilities, Security Hotspots, and Code Smells so you can release quality code every time. Get started analyzing your projects today for free.

  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    There's Clash, which isn't widely used, but is awesome. That said, I come from a traditional software background and have only had to use HDLs for minor tweaks at work. I wonder how the learning curve would be for Firmware Engineers.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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