Clash-ghc Alternatives

clash-ghc reviews and mentions

• C Is Not a Low-Level Language (2018)
  1 project | news.ycombinator.com | 7 Sep 2026

  I've never done verilog professionally but I did "Digital Design and Computer Architecture, RISC-V Edition: RISC-V Edition" as an exercise 2 years ago.

  I would say Verilog is very much NOT a low level language.

  Metaphorically, it feels closer to SQL to me. I mean this in that you theoretically tell the system what it should do, and it builds it into the messy real world. However, the reality is that the planner (sql) or linker/placer/router/whatever (verilog) are very good, but you often end up needing to actually fully understand the problem anyway when things don't work in the abstract.

  I know there is https://clash-lang.org/ for Verilog design, which sounds a little like what you are talking about (never really looked at it myself).

• VHDL's Crown Jewel
  4 projects | news.ycombinator.com | 30 Mar 2026

  maybe clash [1] would be interesting to you then?

  [1] https://clash-lang.org/

• FPGAs Need a New Future
  5 projects | news.ycombinator.com | 22 Dec 2025

  https://clash-lang.org/ we've already done the research! Circuits are just functional programming (the vast majority of the time).

  We just need the toolchains to be opened up.

• Spade Hardware Description Language
  4 projects | news.ycombinator.com | 12 May 2025

  I thought that this was about the hardware description language Clash developed by some ex-colleagues, but it appeared to be something else. Clash [1] is based on the functional programming language Haskell and it can output to VHDL, Verilog, or SystemVerilog.

  Although the last official release mentioned on the website is from 2021, it is still actively developed on GitHub [2]. See also contranomy [3] for a non-pipelined RV32I RISC-V core written in Clash.

  [1] https://clash-lang.org/

  [2] https://github.com/clash-lang/clash-compiler

  [3] https://github.com/christiaanb/contranomy

• XiangShan – open-source high performance RISC-V processor
  5 projects | news.ycombinator.com | 2 Jan 2025

  What has changed that they are now ripe for disruption? My BSc thesis supervisor runs a company that tries to disrupt Verilog and VHDL and they've been at it for well over a decade. I don't think they're making much of a dent yet but I didn't keep up with the space: https://github.com/clash-lang/clash-compiler. There's also a RISCV implementation written in it.

  All the tooling in this space is so expensive to build and expensive to verify, with such a small market that it seems almost impossible for something to ever challenge the incumbent ecosystems in a reasonable span of time.

• Clash: A Functional Hardware Description Language
  2 projects | news.ycombinator.com | 27 Dec 2023
• Clash (Haskell) for ASIC design
  1 project | /r/chipdesign | 7 Oct 2023
• Building a Networked Key-Value-Store on an FPGA
  1 project | news.ycombinator.com | 19 Jun 2023

  > You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.

  As is Clash :) https://clash-lang.org/

• Need project idea
  4 projects | /r/haskell | 6 Jun 2023

  You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/

• 5 layered CNN implementation on arduino/FPGAs [P]
  4 projects | /r/MachineLearning | 11 May 2023

  I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org

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