SDRAM_Controller_Verilog VS darkriscv

Compare SDRAM_Controller_Verilog vs darkriscv and see what are their differences.

SDRAM_Controller_Verilog

This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz. (by RichardPar)
Verilog mt48lc32m16 sdram
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darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
Riscv processor-design Rv32i rv32e Verilog risc-v Fpga Rtl softcore Core Processor Cpu
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SDRAM_Controller_Verilog darkriscv
- 3
4 1,892
- 1.7%
0.0 6.3
about 3 years ago 13 days ago
Verilog Verilog
- BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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SDRAM_Controller_Verilog

Posts with mentions or reviews of SDRAM_Controller_Verilog. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning SDRAM_Controller_Verilog yet.
Tracking mentions began in Dec 2020.

darkriscv

Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.

What are some alternatives?

When comparing SDRAM_Controller_Verilog and darkriscv you can also consider the following projects:

FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s

biriscv - 32-bit Superscalar RISC-V CPU

open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

XiangShan - Open-source high-performance RISC-V processor

riscv - RISC-V CPU Core (RV32IM)

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

Cores-VeeR-EH1 - VeeR EH1 core

friscv - RISCV CPU implementation in SystemVerilog

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog

SDRAM_Controller_Verilog vs FPGA_SDRAM_Controller darkriscv vs biriscv SDRAM_Controller_Verilog vs open-fpga-verilog-tutorial darkriscv vs XiangShan darkriscv vs riscv darkriscv vs VexRiscv darkriscv vs Cores-VeeR-EH1 darkriscv vs friscv darkriscv vs meta-riscv darkriscv vs f4pga-examples darkriscv vs open-fpga-verilog-tutorial darkriscv vs ice-chips-verilog