Hazard3
darkriscv
| Hazard3 | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 70 | 1,900 | |
| - | 2.2% | |
| 7.2 | 6.3 | |
| 5 days ago | 29 days ago | |
| Verilog | Verilog | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
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Hazard3
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
biriscv - 32-bit Superscalar RISC-V CPU
oblivious-cpu - A re-implementation of ShapeCPU
XiangShan - Open-source high-performance RISC-V processor
fpga_riscv_cpu - fpga verilog risc-v rv32i cpu
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools