Hazard3
3-stage RV32IMACZb* processor with debug (by Wren6991)
fpga_riscv_cpu
fpga verilog risc-v rv32i cpu (by nobotro)
Hazard3 | fpga_riscv_cpu | |
---|---|---|
1 | 1 | |
70 | 8 | |
- | - | |
7.2 | 1.1 | |
5 days ago | about 1 year ago | |
Verilog | Verilog | |
Apache License 2.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Hazard3
Posts with mentions or reviews of Hazard3.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-06.
fpga_riscv_cpu
Posts with mentions or reviews of fpga_riscv_cpu.
We have used some of these posts to build our list of alternatives
and similar projects.
What are some alternatives?
When comparing Hazard3 and fpga_riscv_cpu you can also consider the following projects:
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
oblivious-cpu - A re-implementation of ShapeCPU
friscv - RISCV CPU implementation in SystemVerilog
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!