Hazard3
3-stage RV32IMACZb* processor with debug (by Wren6991)
oblivious-cpu
A re-implementation of ShapeCPU (by mmastrac)
| Hazard3 | oblivious-cpu | |
|---|---|---|
| 1 | 2 | |
| 70 | 18 | |
| - | - | |
| 7.2 | 10.0 | |
| 5 days ago | almost 2 years ago | |
| Verilog | Java | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Hazard3
Posts with mentions or reviews of Hazard3.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-06.
oblivious-cpu
Posts with mentions or reviews of oblivious-cpu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-06.
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Concrete: A fully homomorphic encryption compiler
I started working on a CPU that was designed for FHE about 10 years ago, inspired by the ShapeCPU paper around that time [1] [2]
[1] https://github.com/mmastrac/oblivious-cpu
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Open Source CPU Projects
https://github.com/mmastrac/oblivious-cpu has some implemented in a custom Java RTL. I've been meaning to port to an FPGA at some point.
What are some alternatives?
When comparing Hazard3 and oblivious-cpu you can also consider the following projects:
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
fpga_riscv_cpu - fpga verilog risc-v rv32i cpu