uhd
The USRP™ Hardware Driver Repository (by EttusResearch)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
uhd | darkriscv | |
---|---|---|
3 | 3 | |
918 | 1,892 | |
1.5% | 1.7% | |
9.5 | 6.3 | |
7 days ago | 17 days ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
uhd
Posts with mentions or reviews of uhd.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-02-10.
- USRP Low Band Center Frequency Shift
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Adding patches upstream
Go upstream and first check that your work hasn't already been done. It is common for users to find bugs in a release and fix them, so it might already be patched or have a pull request. If not, go ahead and read/follow the coding and contributing docs.
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[OC] Visualizing the header/symbol dependencies on a single Cpp source file (out of 733 total C/C++ source code files in framework)
There's over 2000 files related to C/C++ software in this framework alone. The amount of organization, effort, and planning it takes to create large frameworks like this is hard to dismiss. Files can easily be in the thousands of lines long, at each little node on the screen.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing uhd and darkriscv you can also consider the following projects:
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
biriscv - 32-bit Superscalar RISC-V CPU
riscv - RISC-V CPU Core (RV32IM)
XiangShan - Open-source high-performance RISC-V processor
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
hdl - HDL libraries and projects
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.