uhd
hdl
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| uhd | hdl | |
|---|---|---|
| 3 | 5 | |
| 908 | 1,374 | |
| 2.3% | 3.3% | |
| 9.4 | 9.0 | |
| 8 days ago | about 14 hours ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
uhd
- USRP Low Band Center Frequency Shift
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Adding patches upstream
Go upstream and first check that your work hasn't already been done. It is common for users to find bugs in a release and fix them, so it might already be patched or have a pull request. If not, go ahead and read/follow the coding and contributing docs.
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[OC] Visualizing the header/symbol dependencies on a single Cpp source file (out of 733 total C/C++ source code files in framework)
There's over 2000 files related to C/C++ software in this framework alone. The amount of organization, effort, and planning it takes to create large frameworks like this is hard to dismiss. Files can easily be in the thousands of lines long, at each little node on the screen.
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
riscv - RISC-V CPU Core (RV32IM)
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
USB_C_Industrial_Camera_FPGA_USB3 - Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.