uhd
riscv
| uhd | riscv | |
|---|---|---|
| 3 | 2 | |
| 913 | 1,040 | |
| 1.0% | - | |
| 9.5 | 1.8 | |
| 13 days ago | over 2 years ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
uhd
- USRP Low Band Center Frequency Shift
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Adding patches upstream
Go upstream and first check that your work hasn't already been done. It is common for users to find bugs in a release and fix them, so it might already be patched or have a pull request. If not, go ahead and read/follow the coding and contributing docs.
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[OC] Visualizing the header/symbol dependencies on a single Cpp source file (out of 733 total C/C++ source code files in framework)
There's over 2000 files related to C/C++ software in this framework alone. The amount of organization, effort, and planning it takes to create large frameworks like this is hard to dismiss. Files can easily be in the thousands of lines long, at each little node on the screen.
riscv
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
biriscv - 32-bit Superscalar RISC-V CPU
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
hdl - HDL libraries and projects
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu - A small, light weight, RISC CPU soft core
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
dpll - A collection of phase locked loop (PLL) related projects