riscv
dpll
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riscv | dpll | |
---|---|---|
2 | 2 | |
1,040 | 87 | |
- | - | |
1.8 | 2.8 | |
over 2 years ago | 3 months ago | |
Verilog | Verilog | |
BSD 3-clause "New" or "Revised" License | - |
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riscv
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Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
dpll
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PLL simulation in Vivado
For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
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Digital Loop Filter for Digital PLL Design
Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
vgasim - A Video display simulator
zipcpu - A small, light weight, RISC CPU soft core
zbasic - A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
wbscope - A wishbone controlled scope for FPGA's
uhd - The USRP™ Hardware Driver Repository
wbuart32 - A simple, basic, formally verified UART controller