dpll
zbasic
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dpll
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PLL simulation in Vivado
For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
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Digital Loop Filter for Digital PLL Design
Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.
zbasic
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AXI Quad SPI 3.2 Flash programming scripts
Here's sort of a generic repo you can look at which might give you some ideas.
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How do you successfully compile a working verilator package on Ubuntu?
Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
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Need help with Objcopy for Verilog Hex File
As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
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How can I get Verilator to Prompt for User Input?
The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.
What are some alternatives?
riscv - RISC-V CPU Core (RV32IM)
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
openarty - An Open Source configuration of the Arty platform
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing
qspiflash - A set of Wishbone Controlled SPI Flash Controllers
vgasim - A Video display simulator
fpga_quick_ram_update - Quickly update a bitstream with new RAM contents
wbscope - A wishbone controlled scope for FPGA's
arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board
wbuart32 - A simple, basic, formally verified UART controller
dspfilters - A collection of demonstration digital filters