dpll VS riscv

Compare dpll vs riscv and see what are their differences.

dpll

A collection of phase locked loop (PLL) related projects (by ZipCPU)
Verilog pll Verilator Fpga Gplv3
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riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
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dpll riscv
2 2
88 1,040
- -
2.8 1.8
4 months ago over 2 years ago
Verilog Verilog
- BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

dpll

Posts with mentions or reviews of dpll. We have used some of these posts to build our list of alternatives and similar projects.
  • PLL simulation in Vivado
    1 project | /r/FPGA | 10 Aug 2022
    For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
  • Digital Loop Filter for Digital PLL Design
    1 project | /r/chipdesign | 25 Jan 2021
    Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing dpll and riscv you can also consider the following projects:

sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces

biriscv - 32-bit Superscalar RISC-V CPU

interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

vgasim - A Video display simulator

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zbasic - A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

zipcpu - A small, light weight, RISC CPU soft core

wbscope - A wishbone controlled scope for FPGA's

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

wbuart32 - A simple, basic, formally verified UART controller

uhd - The USRP™ Hardware Driver Repository

dpll vs sdspi riscv vs biriscv dpll vs interpolation riscv vs openlane dpll vs vgasim riscv vs darkriscv dpll vs zbasic riscv vs zipcpu dpll vs wbscope riscv vs Toast-RV32i dpll vs wbuart32 riscv vs uhd