zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (by ZipCPU)
openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)
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zbasic | openlane | |
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4 | 12 | |
40 | 1,179 | |
- | 5.2% | |
0.0 | 8.4 | |
over 1 year ago | 6 days ago | |
Verilog | Python | |
- | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
zbasic
Posts with mentions or reviews of zbasic.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-01-10.
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AXI Quad SPI 3.2 Flash programming scripts
Here's sort of a generic repo you can look at which might give you some ideas.
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How do you successfully compile a working verilator package on Ubuntu?
Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
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Need help with Objcopy for Verilog Hex File
As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
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How can I get Verilator to Prompt for User Input?
The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.
openlane
Posts with mentions or reviews of openlane.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-04-15.
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[D][P] Represent Analog Circuits as Graphs
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
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how small team survive from cadence cost
There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
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VLSI Tools
OpenLane
- Compiling Code into Silicon
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Kickstarting IC design
And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
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How are modern processors and their architecture designed?
For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
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Project Ideas for Uni
Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
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ASIC design post layout for padding.
I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
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Resources for a physical design engineer
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
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Intro into chip design
https://github.com/efabless/openlane The README is very helpful
What are some alternatives?
When comparing zbasic and openlane you can also consider the following projects:
dpll - A collection of phase locked loop (PLL) related projects
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
openarty - An Open Source configuration of the Arty platform
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
qspiflash - A set of Wishbone Controlled SPI Flash Controllers
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
fpga_quick_ram_update - Quickly update a bitstream with new RAM contents
rocket-chip - Rocket Chip Generator
arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
riscv - RISC-V CPU Core (RV32IM)
opentitan - OpenTitan: Open source silicon root of trust