How are modern processors and their architecture designed?

• openlane

  12 1,174 8.6 Python

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  

For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane

• skywater-pdk

  27 2,830 2.3 Python

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  

You always need a description of the actual silicon used for the RTL-to-GDS flow. This is the PDK. Currently there is AFAIK only one open source PDK available, typically companies are very strict about giving information to third parties. But the Skywater 130nm PDK really gives you a chance to look into, and freely work and design ICs with it: https://github.com/google/skywater-pdk

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• picorv32

  15 2,770 5.2 Verilog

  PicoRV32 - A Size-Optimized RISC-V CPU

  

• rocket-chip

  12 3,002 8.3 Scala

  Rocket Chip Generator

  

More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip

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