openlane VS skywater-pdk

I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.

There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane

OpenLane

And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane

For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane

Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.

I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane

Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter

https://github.com/efabless/openlane The README is very helpful

Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.

https://github.com/google/skywater-pdk

It looks neat, but the process node is 1 um with 3 metal layers.

The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)

From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup.

Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk

If you need a free PDK, check out: https://github.com/google/skywater-pdk

That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130.

https://github.com/google/skywater-pdk

One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.

https://www.digikey.com/en/products/detail/excelitas-technol...

One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it.

https://www.digikey.com/en/products/detail/panasonic-electro...

https://github.com/IdleHandsProject/diycamera (digiOBSCURA)

One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer

https://tinytapeout.com/

Unlike x86_64 which can only legally be produced by two and one-quarter companies, RISC-V is a permissively open-sourced ISA so anyone can make a chip. Literally, you can download Verilog of Berkeley Rocket cores from Github and run it on an FPGA, or prep it to send to SkyWater to fab at 130nm.

Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk).

In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).