skywater-pdk VS Verilog.jl

Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.

https://github.com/google/skywater-pdk

It looks neat, but the process node is 1 um with 3 metal layers.

The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)

From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup.

Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk

If you need a free PDK, check out: https://github.com/google/skywater-pdk

That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130.

https://github.com/google/skywater-pdk

One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.

https://www.digikey.com/en/products/detail/excelitas-technol...

One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it.

https://www.digikey.com/en/products/detail/panasonic-electro...

https://github.com/IdleHandsProject/diycamera (digiOBSCURA)

One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer

https://tinytapeout.com/

Unlike x86_64 which can only legally be produced by two and one-quarter companies, RISC-V is a permissively open-sourced ISA so anyone can make a chip. Literally, you can download Verilog of Berkeley Rocket cores from Github and run it on an FPGA, or prep it to send to SkyWater to fab at 130nm.

Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk).

In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).

It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.

https://github.com/interplanetary-robot/Verilog.jl

Of course, gaining traction on something like this is tricky.

I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.

A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl