Verilog.jl Alternatives

Similar projects and alternatives to Verilog.jl

• skywater-pdk

  27 2,841 2.3 Python Verilog.jl VS skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  

• chisel

  25 3,722 9.7 Scala Verilog.jl VS chisel

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• Octavian.jl

  17 222 3.9 Julia Verilog.jl VS Octavian.jl

  Multi-threaded BLAS-like library that provides pure Julia matrix multiplication

  

• openlane

  12 1,191 8.4 Python Verilog.jl VS openlane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  

• myhdl

  15 1,008 5.1 Python Verilog.jl VS myhdl

  The MyHDL development repository

  

• opentitan

  14 2,365 10.0 SystemVerilog Verilog.jl VS opentitan

  OpenTitan: Open source silicon root of trust

  

• RecursiveFactorization.jl

  8 74 6.1 Julia Verilog.jl VS RecursiveFactorization.jl
  

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

• Modia.jl

  4 318 6.7 Julia Verilog.jl VS Modia.jl

  Modeling and simulation of multidomain engineering systems

  

• svls

  3 414 8.1 Rust Verilog.jl VS svls

  SystemVerilog language server

• Automa.jl

  2 176 7.0 Julia Verilog.jl VS Automa.jl

  A julia code generator for regular expressions

  

• circt

  6 1,527 9.9 C++ Verilog.jl VS circt

  Circuit IR Compilers and Tools

  

• freepdk-45nm

  1 108 10.0 Verilog Verilog.jl VS freepdk-45nm

  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

  

• edalize

  4 593 7.2 Python Verilog.jl VS edalize

  An abstraction library for interfacing EDA tools

• zerosoc

  2 49 7.2 SystemVerilog Verilog.jl VS zerosoc

  Demo SoC for SiliconCompiler.

  

• gssi

  1 3 10.0 TeX Verilog.jl VS gssi

  Stuff I worked on while at GSSI (L'Aquila, Italy)

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives