openlane VS freepdk-45nm

Compare openlane vs freepdk-45nm and see what are their differences.

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen (by mflowgen)
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openlane freepdk-45nm
12 1
1,174 108
4.8% 11.1%
8.6 10.0
7 days ago about 4 years ago
Python Verilog
Apache License 2.0 -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

openlane

Posts with mentions or reviews of openlane. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-15.
  • [D][P] Represent Analog Circuits as Graphs
    3 projects | /r/MachineLearning | 15 Apr 2023
    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
  • how small team survive from cadence cost
    1 project | /r/chipdesign | 15 Jan 2023
    There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
  • VLSI Tools
    6 projects | /r/chipdesign | 14 Dec 2022
    OpenLane
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
  • Kickstarting IC design
    2 projects | /r/chipdesign | 3 Dec 2021
    And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
  • How are modern processors and their architecture designed?
    4 projects | /r/ECE | 28 Sep 2021
    For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
  • Project Ideas for Uni
    2 projects | /r/FPGA | 23 Aug 2021
    Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
  • ASIC design post layout for padding.
    1 project | /r/chipdesign | 15 Aug 2021
    I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
  • Resources for a physical design engineer
    1 project | /r/chipdesign | 20 Jul 2021
    Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
  • Intro into chip design
    1 project | /r/chipdesign | 7 May 2021
    https://github.com/efabless/openlane The README is very helpful

freepdk-45nm

Posts with mentions or reviews of freepdk-45nm. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-12-07.
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
    Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).

    Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]

    If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.

    [0] https://github.com/mflowgen/freepdk-45nm

What are some alternatives?

When comparing openlane and freepdk-45nm you can also consider the following projects:

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

edalize - An abstraction library for interfacing EDA tools

rocket-chip - Rocket Chip Generator

Verilog.jl - Verilog for Julia

NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上

opentitan - OpenTitan: Open source silicon root of trust

riscv - RISC-V CPU Core (RV32IM)

chisel - Chisel: A Modern Hardware Design Language

zerosoc - Demo SoC for SiliconCompiler.