zbasic VS dpll

Compare zbasic vs dpll and see what are their differences.

zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (by ZipCPU)

dpll

A collection of phase locked loop (PLL) related projects (by ZipCPU)
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zbasic dpll
4 2
40 87
- -
0.0 2.8
over 1 year ago 3 months ago
Verilog Verilog
- -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

zbasic

Posts with mentions or reviews of zbasic. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-01-10.
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's sort of a generic repo you can look at which might give you some ideas.
  • How do you successfully compile a working verilator package on Ubuntu?
    1 project | /r/ZipCPU | 27 Jul 2021
    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
  • Need help with Objcopy for Verilog Hex File
    3 projects | /r/FPGA | 7 Jul 2021
    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
  • How can I get Verilator to Prompt for User Input?
    3 projects | /r/FPGA | 19 Apr 2021
    The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.

dpll

Posts with mentions or reviews of dpll. We have used some of these posts to build our list of alternatives and similar projects.
  • PLL simulation in Vivado
    1 project | /r/FPGA | 10 Aug 2022
    For an example of a simple digital PLL that you could modify for this purpose, check out this article discussing this logic.
  • Digital Loop Filter for Digital PLL Design
    1 project | /r/chipdesign | 25 Jan 2021
    Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.

What are some alternatives?

When comparing zbasic and dpll you can also consider the following projects:

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

riscv - RISC-V CPU Core (RV32IM)

openarty - An Open Source configuration of the Arty platform

sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces

qspiflash - A set of Wishbone Controlled SPI Flash Controllers

interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing

fpga_quick_ram_update - Quickly update a bitstream with new RAM contents

vgasim - A Video display simulator

arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board

wbscope - A wishbone controlled scope for FPGA's

wbuart32 - A simple, basic, formally verified UART controller

dspfilters - A collection of demonstration digital filters