ice40_power
darkriscv
| ice40_power | darkriscv | |
|---|---|---|
| 2 | 3 | |
| 20 | 1,892 | |
| - | 1.7% | |
| 0.0 | 6.3 | |
| over 3 years ago | 14 days ago | |
| Verilog | Verilog | |
| MIT License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ice40_power
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iCE40 power consumption question
You can probably extrapolate from the numbers here.
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Using an FPGA for low-power device with fast image acquisition
Aside from the points that /u/captain_wiggles_ pointed out, this is an application which ice40 FPGAs were actually designed for. They are low power (example) and have some features specifically designed for video applications, such as (sub)LVDS inputs and "outputs." Depending on your specs, one of these FPGAs could be a good choice (and you get a nice FOSS toochain as a bonus).
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
riscv - RISC-V CPU Core (RV32IM)
biriscv - 32-bit Superscalar RISC-V CPU
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
XiangShan - Open-source high-performance RISC-V processor
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog