FPGA-SDcard-Reader
darkriscv
| FPGA-SDcard-Reader | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 221 | 1,905 | |
| - | 2.4% | |
| 3.8 | 6.3 | |
| 8 months ago | 2 days ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
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FPGA-SDcard-Reader
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
biriscv - 32-bit Superscalar RISC-V CPU
rggen - Code generation tool for control and status registers
XiangShan - Open-source high-performance RISC-V processor
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
riscv - RISC-V CPU Core (RV32IM)
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture