FPGA-SDcard-Reader
axi
FPGA-SDcard-Reader | axi | |
---|---|---|
1 | 3 | |
217 | 937 | |
- | 3.7% | |
3.8 | 6.1 | |
8 months ago | 13 days ago | |
Verilog | SystemVerilog | |
GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
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FPGA-SDcard-Reader
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
chisel - Chisel: A Modern Hardware Design Language
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
rggen - Code generation tool for control and status registers
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opentitan - OpenTitan: Open source silicon root of trust
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
Cores-VeeR-EL2 - VeeR EL2 Core