FPGA-SDcard-Reader
open-register-design-tool
| FPGA-SDcard-Reader | open-register-design-tool | |
|---|---|---|
| 1 | 2 | |
| 217 | 182 | |
| - | 1.6% | |
| 3.8 | 5.3 | |
| 8 months ago | 10 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 only | Apache License 2.0 |
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FPGA-SDcard-Reader
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
rggen - Code generation tool for control and status registers
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
biriscv - 32-bit Superscalar RISC-V CPU