kianRiscV
darkriscv
| kianRiscV | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 492 | 1,900 | |
| - | 2.2% | |
| 7.8 | 6.3 | |
| 5 days ago | 28 days ago | |
| AGS Script | Verilog | |
| ISC License | BSD 3-clause "New" or "Revised" License |
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kianRiscV
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Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
XiangShan - Open-source high-performance RISC-V processor
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
riscv - RISC-V CPU Core (RV32IM)
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
Cores-VeeR-EH1 - VeeR EH1 core
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
friscv - RISCV CPU implementation in SystemVerilog