kianRiscV
s1-ecg-demo
| kianRiscV | s1-ecg-demo | |
|---|---|---|
| 1 | 2 | |
| 492 | 11 | |
| - | - | |
| 7.8 | 0.0 | |
| 5 days ago | over 1 year ago | |
| AGS Script | AGS Script | |
| ISC License | CERN Open Hardware Licence Version 2 - Permissive |
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kianRiscV
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Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
s1-ecg-demo
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Designed an ECG dev kit with Bluetooth & FPGA
Here you go 😊 https://github.com/siliconwitchery/s1-ecg-demo
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
openemr - The most popular open source electronic health records and medical practice management solution.
my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
brainflow - BrainFlow is a library intended to obtain, parse and analyze EEG, EMG, ECG and other kinds of data from biosensors
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
BioAmp-EXG-Pill - BioAmp EXG Pill is a small and elegant Analog Front End (AFE) board for BioPotential signal acquisition.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
MobilECG-II - Open source ECG holter
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
NeuroKit - NeuroKit2: The Python Toolbox for Neurophysiological Signal Processing
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation