kianRiscV

RISC-V Linux SoC, marchID: 0x2b (by splinedrive)

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  • Have I discovered a synthesis/routing defect with the Gowin IDE?
    1 project | /r/GowinFPGA | 22 Jul 2023
    I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.

Stats

Basic kianRiscV repo stats
1
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8.2
26 days ago

splinedrive/kianRiscV is an open source project licensed under ISC License which is an OSI approved license.

The primary programming language of kianRiscV is Verilog.


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Did you know that Verilog is
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