kianRiscV VS riscv

Compare kianRiscV vs riscv and see what are their differences.

kianRiscV

RISC-V Linux SoC, marchID: 0x2b (by splinedrive)
Riscv Rv32im Verilog Fpga icebreaker ice40 ecp5 icoboard ulx3s icefun multiplier divider Cpu softcpu ice40hx1k pipelined linuxsoc Linux
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riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
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kianRiscV riscv
1 2
492 1,040
- -
7.8 1.8
5 days ago over 2 years ago
AGS Script Verilog
ISC License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

kianRiscV

Posts with mentions or reviews of kianRiscV. We have used some of these posts to build our list of alternatives and similar projects.
  • Have I discovered a synthesis/routing defect with the Gowin IDE?
    1 project | /r/GowinFPGA | 22 Jul 2023
    I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing kianRiscV and riscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

icicle - 32-bit RISC-V system on chip for iCE40 FPGAs

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zipcpu - A small, light weight, RISC CPU soft core

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.

uhd - The USRP™ Hardware Driver Repository

kianRiscV vs biriscv riscv vs biriscv kianRiscV vs my_hdmi_device riscv vs openlane kianRiscV vs icicle riscv vs darkriscv kianRiscV vs darkriscv riscv vs zipcpu kianRiscV vs neorv32 riscv vs Toast-RV32i kianRiscV vs s1-ecg-demo riscv vs uhd