kianRiscV
my_hdmi_device
| kianRiscV | my_hdmi_device | |
|---|---|---|
| 1 | 1 | |
| 492 | 85 | |
| - | - | |
| 7.8 | 0.0 | |
| 5 days ago | 7 months ago | |
| AGS Script | GLSL | |
| ISC License | ISC License |
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kianRiscV
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Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
my_hdmi_device
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How do I set up a clock source on a GoWin FPGA?
I assume you encountered the IPs provided by Gowin for both DVI and video framebuffer, I saw an open source implementation of DVI which now supports the Nano 4k. Haven't tried it and I assume you want to make it from scratch, but it's nice to have just in case.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
ULX3S_FPGA_Sobel_Edge_Detection_OV7670 - Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
nano4k_hdmi_tx - Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv - RISC-V CPU Core (RV32IM)