kianRiscV
icicle
| kianRiscV | icicle | |
|---|---|---|
| 1 | 1 | |
| 492 | 284 | |
| - | - | |
| 7.8 | 6.0 | |
| 5 days ago | 12 months ago | |
| AGS Script | Python | |
| ISC License | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
kianRiscV
-
Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
icicle
-
"AMD Extends the UltraScale+ Product Portfolio"
If you just need a system to practice VHDL / Verilog on, the $50 entry point is a bit better. It won't be fast or big, but there's plenty to do and learn on something like that. The ICE40 is large enough to get a RISCV core for example.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv - RISC-V CPU Core (RV32IM)