AGS Script Verilog Projects
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s1-ecg-demo
An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
Project mention: Have I discovered a synthesis/routing defect with the Gowin IDE? | /r/GowinFPGA | 2023-07-22I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
Index
| Project | Stars | |
|---|---|---|
| 1 | kianRiscV | 481 |
| 2 | s1-ecg-demo | 11 |
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