FPGA_NTP_SERVER
A FPGA implementation of the NTP and NTS protocols (by Netnod)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| FPGA_NTP_SERVER | darkriscv | |
|---|---|---|
| 2 | 3 | |
| 49 | 1,897 | |
| - | 2.0% | |
| 3.1 | 6.3 | |
| 11 months ago | 20 days ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_NTP_SERVER
Posts with mentions or reviews of FPGA_NTP_SERVER.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-02-15.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing FPGA_NTP_SERVER and darkriscv you can also consider the following projects:
ha1588 - Hardware Assisted IEEE 1588 IP Core
biriscv - 32-bit Superscalar RISC-V CPU
raspberrypi-ptp - How to run IEEE-1588 on RaspberryPi hardware
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
FPGA_NTP_SERVER vs ha1588
darkriscv vs biriscv
FPGA_NTP_SERVER vs raspberrypi-ptp
darkriscv vs XiangShan
FPGA_NTP_SERVER vs riscv
darkriscv vs riscv
darkriscv vs VexRiscv
darkriscv vs Cores-VeeR-EH1
darkriscv vs friscv
darkriscv vs meta-riscv
darkriscv vs f4pga-examples
darkriscv vs open-fpga-verilog-tutorial