OpenROAD-flow-scripts
darkriscv
| OpenROAD-flow-scripts | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 258 | 1,897 | |
| 3.9% | 2.0% | |
| 9.8 | 6.3 | |
| 6 days ago | 20 days ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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OpenROAD-flow-scripts
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VLSI Tools
OpenROAD-flow-scripts
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
biriscv - 32-bit Superscalar RISC-V CPU
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
XiangShan - Open-source high-performance RISC-V processor
siliconcompiler - A modular build system for hardware
riscv - RISC-V CPU Core (RV32IM)
hammer - Hammer: Highly Agile Masks Made Effortlessly from RTL
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
caravel_fulgor_opamp - Test Chip General Purpose OpAmp using Skywater SKY130 PDK
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture