Cores-VeeR-EL2
axi
Cores-VeeR-EL2 | axi | |
---|---|---|
1 | 3 | |
222 | 930 | |
0.9% | 3.0% | |
9.0 | 6.1 | |
7 days ago | 8 days ago | |
SystemVerilog | SystemVerilog | |
Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Cores-VeeR-EL2
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
chisel - Chisel: A Modern Hardware Design Language
Cores-VeeR-EH1 - VeeR EH1 core
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
opentitan - OpenTitan: Open source silicon root of trust
rocket-chip - Rocket Chip Generator
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL