Cores-VeeR-EL2 VS axi

Compare Cores-VeeR-EL2 vs axi and see what are their differences.

Cores-VeeR-EL2

VeeR EL2 Core (by chipsalliance)
el2 Verilator western-digital Riscv risc-v Processor open-source-hardware Fusesoc Rtl Fpga Axi4 ahb-lite Riscv32 asic-design
Source Code
chipsalliance.github.io
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
Source Code
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Cores-VeeR-EL2 axi
1 3
222 930
0.9% 3.0%
9.0 6.1
6 days ago 8 days ago
SystemVerilog SystemVerilog
Apache License 2.0 GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

Cores-VeeR-EL2

Posts with mentions or reviews of Cores-VeeR-EL2. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-09-08.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing Cores-VeeR-EL2 and axi you can also consider the following projects:

riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine

chisel - Chisel: A Modern Hardware Design Language

Cores-VeeR-EH1 - VeeR EH1 core

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

opentitan - OpenTitan: Open source silicon root of trust

rocket-chip - Rocket Chip Generator

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

Cores-VeeR-EL2 vs riscv-boom axi vs chisel Cores-VeeR-EL2 vs Cores-VeeR-EH1 axi vs nmigen Cores-VeeR-EL2 vs projf-explore axi vs fusesoc Cores-VeeR-EL2 vs cv32e40p axi vs opentitan Cores-VeeR-EL2 vs rocket-chip axi vs qemu Cores-VeeR-EL2 vs VeriGPU axi vs Pyverilog