Cores-VeeR-EH1
rocket-chip
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Cores-VeeR-EH1 | rocket-chip | |
---|---|---|
8 | 12 | |
773 | 3,002 | |
1.6% | 2.1% | |
0.0 | 8.3 | |
11 months ago | 7 days ago | |
SystemVerilog | Scala | |
Apache License 2.0 | GNU General Public License v3.0 or later |
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Cores-VeeR-EH1
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Looking for a RISC-V core for verification
SweRV EH1 comes with a verilator testbench that can run compiled instructions. You'll need to expand on it if you want things like external memory etc.
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Nvidia: GPUs can do better chip design in a few days than 10 man year
together foundations and the use domains of chip design, networks and robotics; (iii) the cycle of translation and impact brings research and the leading edge of practice closer together; and (iv) the cycle of research, education, and broadening participation grows the field and its workforce.*
The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.
There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.
I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.
[1] https://theopenroadproject.org/news/leveling-up-a-trajectory...
[2] https://opentitan.org/
[3] https://github.com/chipsalliance/Cores-SweRV
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Is a single cycle CPU of any use besides learning?
Absolutely! I have no illusions that I'll build anything even remotely comparable to a commercial core. I had a look at the features of the WD SweRV core and the complexity simply blows my mind, I don't think I'll get there any time soon. This is purely for fun, but it will be much more satisfying if I can start using the CPU I designed in my tiny personal IoT projects. Hence the question, at what point can I start finding some use for it. Maybe an arduino replacement?
- How does philosophy of open source hardware react to "dominant" chip makers?
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
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Nvidia's ownership of ARM could drive customers to RISC-V, other alternatives if not careful, says Xilinx CEO
This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.
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About RISC-V becoming so popular as ARM for Embedded Systems
Per your last point, I believe this is the most important one. Big vendors like WD can just design their own core and plop it down in all of their hard drives that ship in large volumes. They even share their RTL.
rocket-chip
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
[1] https://github.com/chipsalliance/rocket-chip
- Can anyone explain simply how OpenSource the RISC-V actually is?
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Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
- FPGA for RISC-V Processor
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How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
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Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
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The First Affordable RISC-V Computer Designed to Run Linux
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Cores-VeeR-EL2 - VeeR EL2 Core
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development