Cores-VeeR-EH1 VS RISC-V-Guide

SweRV EH1 comes with a verilator testbench that can run compiled instructions. You'll need to expand on it if you want things like external memory etc.

together foundations and the use domains of chip design, networks and robotics; (iii) the cycle of translation and impact brings research and the leading edge of practice closer together; and (iv) the cycle of research, education, and broadening participation grows the field and its workforce.*

The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.

There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.

I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.

[1] https://theopenroadproject.org/news/leveling-up-a-trajectory...

[2] https://opentitan.org/

[3] https://github.com/chipsalliance/Cores-SweRV

Absolutely! I have no illusions that I'll build anything even remotely comparable to a commercial core. I had a look at the features of the WD SweRV core and the complexity simply blows my mind, I don't think I'll get there any time soon. This is purely for fun, but it will be much more satisfying if I can start using the CPU I designed in my tiny personal IoT projects. Hence the question, at what point can I start finding some use for it. Maybe an arduino replacement?

Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2

This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.

Per your last point, I believe this is the most important one. Big vendors like WD can just design their own core and plop it down in all of their hard drives that ship in large volumes. They even share their RTL.

I know RISC-V has a been around for several years now and companies like Western Digital use it for their NAS products and even Apple has hired a few RISC-V engineers in the past year. Though, what are other peoples experiences with RISC-V engineering and development? Also, for those that haven't heard of RISC-V here some some helpful Tools, Projects, and Learning Resources.

Useful Tools & Resources for RISC-V development.

A useful set of Tools and Learning for RISC-V.

I found a useful list of Tools, Programs, and Resources for RISC-V. Looks like it covers RISC-V models, RISC-V Operating systems, RISC-V Tools, 5G, and Machine Learning. I thought I'd share it for anyone that's interested. https://github.com/mikeroyal/RISC-V-Guide