litex
Build your hardware, easily! (by enjoy-digital)
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
Our great sponsors
| litex | fusesoc | |
|---|---|---|
| 29 | 12 | |
| 2,683 | 1,118 | |
| - | - | |
| 9.7 | 7.3 | |
| 4 days ago | 18 days ago | |
| C | Python | |
| GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
litex
Posts with mentions or reviews of litex.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-11-06.
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
What are some alternatives?
When comparing litex and fusesoc you can also consider the following projects:
nmigen-tutorial - A tutorial for using nmigen
edalize - An abstraction library for interfacing EDA tools
SpinalHDL - Scala based HDL
opentitan - OpenTitan: Open source silicon root of trust
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
verilog-ethernet - Verilog Ethernet components for FPGA implementation
rocket-chip - Rocket Chip Generator
litedram - Small footprint and configurable DRAM core
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.