CPU design for college project

• RISC-V_MYTH_Workshop

  1 75 6.2 TL-Verilog

  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

Check this out: https://github.com/stevehoover/RISC-V_MYTH_Workshop You can design a pipelined RISCV 32 bit ISA architecture microprocessor in 30 hours using TL-Verilog!

• litex

  29 2,683 9.7 C

  Build your hardware, easily!

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

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