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CPU design for college project
2 projects | /r/FPGA | 9 Feb 2023

Check this out: https://github.com/stevehoover/RISC-V_MYTH_Workshop You can design a pipelined RISCV 32 bit ISA architecture microprocessor in 30 hours using TL-Verilog!

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6.2

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4 months ago

stevehoover/RISC-V_MYTH_Workshop is an open source project licensed under The Unlicense which is not an OSI approved license.

The primary programming language of RISC-V_MYTH_Workshop is TL-Verilog.