edalize
serv
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| edalize | serv | |
|---|---|---|
| 4 | 19 | |
| 590 | 1,244 | |
| - | - | |
| 7.3 | 7.7 | |
| 10 days ago | 17 days ago | |
| Python | Verilog | |
| BSD 2-clause "Simplified" License | ISC License |
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edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
serv
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
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Efinix and Xyloni Board - Heard a lot of clients mention them, so took a look.
It will be interesting to see if a Serv will fit with some usable gates left over.
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
IronOS - Open Source Soldering Iron firmware
apio - :seedling: Open source ecosystem for open FPGA boards
icestudio - :snowflake: Visual editor for open FPGA boards
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
rggen - Code generation tool for control and status registers
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA