serv VS fusesoc

Compare serv vs fusesoc and see what are their differences.


SERV - The SErial RISC-V CPU (by olofk)


Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
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serv fusesoc
16 10
911 915
- -
6.5 6.9
about 1 month ago 8 days ago
Verilog Python
ISC License BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of serv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-11.


Posts with mentions or reviews of fusesoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-05-11.

What are some alternatives?

When comparing serv and fusesoc you can also consider the following projects:

litex - Build your hardware, easily!

edalize - An abstraction library for interfacing EDA tools

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

opentitan - OpenTitan: Open source silicon root of trust

neorv32 - 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

VHDL_Lib - Library of VHDL components that are useful in larger designs.

viv-prj-gen - tcl scripts used to build or generate vivado projects automatically

rocket-chip - Rocket Chip Generator

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

hdl - HDL libraries and projects