serv VS riscv-cores-list

Compare serv vs riscv-cores-list and see what are their differences.

serv

SERV - The SErial RISC-V CPU (by olofk)

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs (by riscvarchive)
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serv riscv-cores-list
16 3
911 564
- -
6.5 1.8
about 1 month ago almost 2 years ago
Verilog
ISC License -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

serv

Posts with mentions or reviews of serv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-11.

riscv-cores-list

Posts with mentions or reviews of riscv-cores-list. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-05-18.
  • Looking for a RISC-V core for verification
    3 projects | reddit.com/r/RISCV | 18 May 2022
    I'm planning to start my Master's thesis on RISC-V verification, so I'm looking for a core that I can use to simulate. I came across this list of cores on github and out of these which would you recommend is ideal for my application. I have only worked on ARM cores before in my internship so the designs were already set up by the company there, but now I am having trouble doing this on my own. I decided to go with the Hummingbirdv2 e203 core as I have experience with verilog, but I am unable to even simulate the test code because of some syntax error. Is there someone who has experience using this core before or can recommend some other core that is straightforward with the setup?
  • Capital required to design and manufacture smartphones/computers in US
    3 projects | reddit.com/r/Purism | 21 Jan 2022
    There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)

What are some alternatives?

When comparing serv and riscv-cores-list you can also consider the following projects:

neorv32 - 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

edalize - An abstraction library for interfacing EDA tools

zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure

riscv_verilator_model - RISCV model for Verilator/FPGA targets

ContrAlto - This repository contains the source code for Living Computers: Museum+Labs's Xerox Alto emulator, ContrAlto.

IronOS - Open Source Soldering Iron firmware for Miniware and Pinecil

psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU