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Top 23 risc-v Open-Source Projects
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
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chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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risc0
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
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SaaSHub
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Project mention: Help Needed with Tauri Desktop App for NFC Card Enrollment on ESP32 | /r/tauri | 2023-08-26For the ESP32 in read mode, we've successfully developed a project using PlatformIO that accepts the key during build time and stores it in memory.
Hi! This is Daniel from OxidOS Automotive (stating this for disclaimer purposes).
Yes, our OS is based on TockOS, and our CEO (Alex Radovici) is #7 in the contributors list (https://github.com/tock/tock/graphs/contributors), with other colleagues contributing in the past years.
Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.
Project mention: CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux | news.ycombinator.com | 2023-11-15
Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24
Project mention: Emulating IoT Firmware Made Easy: Start Hacking Without the Physical Device | news.ycombinator.com | 2023-06-18qemu is fine if the IoT device only runs Linux; may want to look into something like https://renode.io/ for a more comprehensive approach.
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
The idea is to write a C++ model that that produces cycle accurate outputs of the branch predictor, core pipeline, queues, memory latency, cache hierarchy, prefetch behaviour, etc. Transistor level accuracy isn't needed as long as the resulting cycle timings are identical or near identical. The improvement in workload runtime compared to a Verilog simulation is precisely because they aren't trying to model every transistor, but just the important parameters which effect performance.
Let's take a simple example: Instead of modeling a 64-bit adder in all its gory transistor level detail, you can just have the model return the correct data after 1 "cycle" or whatever your ALU latency is. As long as that cycle latency is the same as the real hardware, you'll get an accurate performance number.
What's particularly useful about these models is they enable much easier and faster state space exploration to see how a circuit would perform, well before going ahead with the Verilog implementation, which relatively speaking can take circuit designers ages. "How much faster would my CPU be if it had a 20% larger register file" can be answered in a day or two before getting a circuit designer to go try and implement such a thing.
If you want an open source example, take a look at the gem5 project (https://www.gem5.org). It's not quite as sophisticated as the proprietary models used in industry, but it's a used widely in academia and open source hardware design and is a great place to start.
You can actually write zkps in pure Rust, but there's not currently any blockchain integration: https://github.com/risc0/risc0
We've had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex.
An ETH Zurich team have done a triple core lockstep version for cubesats: https://www.theregister.com/2023/10/05/riscv_microcontroller...
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
Project mention: A self-hosting and educational C optimizing compiler | news.ycombinator.com | 2024-01-07Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
risc-v related posts
- Loongson 3A6000: A Star Among Chinese CPUs
- MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
- Ask HN: Are there any open source dual-issue RISC-V processor
- SERV – The SErial RISC-V CPU
- How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
- RISC-V Ox64 BL808 SBC: Starting Apache NuttX Real-Time Operating System
- Ask HN: Looking for a project to volunteer on? (November 2023)
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A note from our sponsor - WorkOS
workos.com | 23 Apr 2024
Index
What are some of the best open-source risc-v projects? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | rt-thread | 9,522 |
| 2 | PlatformIO | 7,509 |
| 3 | tock | 4,971 |
| 4 | DietPi | 4,521 |
| 5 | XiangShan | 4,305 |
| 6 | Ripes | 2,355 |
| 7 | cva6 | 2,074 |
| 8 | reko | 1,959 |
| 9 | darkriscv | 1,882 |
| 10 | neorv32 | 1,415 |
| 11 | renode | 1,411 |
| 12 | chipyard | 1,411 |
| 13 | gem5 | 1,404 |
| 14 | risc0 | 1,371 |
| 15 | serv | 1,244 |
| 16 | ibex | 1,237 |
| 17 | rars | 1,090 |
| 18 | riscv | 1,040 |
| 19 | shecc | 1,038 |
| 20 | RVVM | 807 |
| 21 | scr1 | 775 |
| 22 | Cores-VeeR-EH1 | 773 |
| 23 | biriscv | 749 |
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