Top 23 Asic Open-Source Projects

• skywater-pdk

  27 2,831 2.3 Python

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  

Project mention: Ask HN: Open-Source Simple CPU? | news.ycombinator.com | 2024-03-16

Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.

https://github.com/google/skywater-pdk

• cva6

  10 2,085 9.7 Assembly

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  

Project mention: CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux | news.ycombinator.com | 2023-11-15

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• neorv32

  77 1,423 9.9 C

  :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

• clash-ghc

  33 1,372 9.1 Haskell

  Haskell to VHDL/Verilog/SystemVerilog compiler

  

Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

• serv

  19 1,244 7.7 Verilog

  SERV - The SErial RISC-V CPU

Project mention: SERV – The SErial RISC-V CPU | news.ycombinator.com | 2023-12-10

• openlane

  12 1,179 8.4 Python

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  

• riscv

  2 1,040 1.8 Verilog

  RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• axi

  3 922 6.8 SystemVerilog

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• biriscv

  6 749 0.0 Verilog

  32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• vunit

  10 682 8.2 VHDL

  VUnit is a unit testing framework for VHDL/SystemVerilog

  

• gf180mcu-pdk

  2 337 2.8 Makefile

  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

  

• tensil

  12 319 0.0 Scala

  Open source machine learning accelerators

  

Project mention: Tensil | news.ycombinator.com | 2023-06-22

• ara

  5 304 7.5 C

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core (by pulp-platform)

  

Project mention: x86 vs ARM; Vector and Matrix Extensions; How do they compare? | /r/hardware | 2023-12-09

yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future

• esp

  1 295 7.6 C

  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

  

• surf

  1 285 8.7 VHDL

  A huge VHDL library for FPGA development (by slaclab)

  

• rggen

  3 277 7.7 Ruby

  Code generation tool for control and status registers

  

• mempool

  2 227 8.6 C

  A 256-RISC-V-core system with low-latency access into shared L1 memory. (by pulp-platform)

  

• systemrdl-compiler

  1 222 7.3 Python

  SystemRDL 2.0 language compiler front-end

  

• livehd

  1 197 9.2 Verilog

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• open-register-design-tool

  2 181 5.3 Verilog

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• skillbridge

  1 159 8.1 Python

  A seamless python to Cadence Virtuoso Skill interface

  

• neoTRNG

  10 152 7.5 VHDL

  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06

• pygears

  5 142 0.0 Python

  HW Design: A Functional Approach

• SaaSHub

  www.saashub.com sponsored

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

Asic related posts

• Ask HN: Open-Source Simple CPU?
  1 project | news.ycombinator.com | 16 Mar 2024
• SERV – The SErial RISC-V CPU
  1 project | news.ycombinator.com | 10 Dec 2023
• x86 vs ARM; Vector and Matrix Extensions; How do they compare?
  2 projects | /r/hardware | 9 Dec 2023
• CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
  1 project | news.ycombinator.com | 15 Nov 2023
• Ara2: RVV 1.0 Compliant Open-Source Processor
  1 project | news.ycombinator.com | 15 Nov 2023
• Libre Silicon – Free semiconductors for everyone
  3 projects | news.ycombinator.com | 19 Oct 2023
• Ask HN: How to start a fabless chip company targeting a modern process node?
  1 project | news.ycombinator.com | 10 Jul 2023
• A note from our sponsor - SaaSHub
  www.saashub.com | 26 Apr 2024

  SaaSHub helps you find the best software and product alternatives Learn more →

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