Cva6 Alternatives

cva6 reviews and mentions

• CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
  1 project | news.ycombinator.com | 15 Nov 2023
• Recommendations for RISC-V on FPGA
  7 projects | /r/FPGA | 8 Mar 2023

  Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

• The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
  1 project | news.ycombinator.com | 23 Oct 2022
• Capital required to design and manufacture smartphones/computers in US
  3 projects | /r/Purism | 21 Jan 2022

  There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)

• Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
  2 projects | /r/RISCV | 20 Jan 2022

  The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.

• Some data points on Vivado performance on Ryzen and Alder Lake
  1 project | /r/FPGA | 11 Jan 2022

  I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6

• What is Purism's roadmap for open-source hardware/schematics?
  1 project | /r/Purism | 29 Sep 2021

  When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.

• XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
  2 projects | /r/RISCV | 7 Jul 2021

  Ariane is now cva6 (it moved to a industry supported non-profit).

• How many more years until we have a completely open source RISC-V SOC?
  6 projects | /r/RISCV | 26 May 2021

  At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).

• OpenHW Group and Mitacs announce a $22.5M research program for open-source processors
  1 project | /r/linux | 10 Mar 2021

  Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.

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