Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression. Learn more →
Cva6 Alternatives
Similar projects and alternatives to cva6
-
-
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
-
CodiumAI
TestGPT | Generating meaningful tests for busy devs. Get non-trivial tests (and trivial, too!) suggested right inside your IDE, so you can code smart, create more value, and stay confident when you push.
-
-
-
openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
-
riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
-
-
SonarLint
Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.
-
-
-
-
-
neorv32
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
-
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core (by pulp-platform)
-
-
openfirmware
Open Firmware (IEE1275-1994) implementation by its inventor. (by MitchBradley)
-
gd32vf103inator
Program the GD32VF103 using C, your favourite editor and make
-
InfluxDB
Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
cva6 reviews and mentions
-
Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
-
Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
-
Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
-
XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
-
How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
-
A note from our sponsor - InfluxDB
www.influxdata.com | 31 May 2023
Stats
openhwgroup/cva6 is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of cva6 is SystemVerilog.