Top 23 Systemverilog Open-Source Projects

• clash-ghc

  33 1,372 9.1 Haskell

  Haskell to VHDL/Verilog/SystemVerilog compiler

  

Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

• verible

  6 1,189 9.3 C++

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  

Project mention: How to instance module with auto-completion for verilog in neovim? | /r/neovim | 2023-08-25

I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?

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• hdmi

  7 1,004 4.7 SystemVerilog

  Send video/audio over HDMI on an FPGA

  

Project mention: HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD | news.ycombinator.com | 2024-02-28

Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...

• axi

  3 922 6.8 SystemVerilog

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• edalize

  4 590 7.3 Python

  An abstraction library for interfacing EDA tools

• slang

  4 533 9.7 C++

  SystemVerilog compiler and language services (by MikePopoloski)

• vscode-terosHDL

  3 490 9.2 JavaScript

  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  

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• sv2v

  3 464 7.6 Haskell

  SystemVerilog to Verilog conversion

Project mention: Verilog functions and wires | /r/Verilog | 2023-06-11

I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.

• svls

  3 409 8.2 Rust

  SystemVerilog language server

Project mention: How to configure vim like an IDE | /r/vim | 2023-06-27

svls

• veryl

  7 396 9.7 Rust

  Veryl: A Modern Hardware Description Language

  

Project mention: Veryl: A Modern Hardware Description Language | news.ycombinator.com | 2024-03-12

• sv-parser

  2 375 5.8 Rust

  SystemVerilog parser library fully compliant with IEEE 1800-2017

• pymtl3

  5 348 5.2 Python

  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

  

Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

• Surelog

  1 329 9.4 C++

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)

  

• svlint

  2 281 8.5 Rust

  SystemVerilog linter

Project mention: Veryl: A Modern Hardware Description Language | news.ycombinator.com | 2024-03-12

https://github.com/dalance/svlint

After writing it, I felt that more improvement is difficult because the specification of SystemVerilog is too complicated.

• rggen

  3 277 7.7 Ruby

  Code generation tool for control and status registers

  

• hdlConvertor

  1 264 5.8 C++

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

• FPGA-SDcard-Reader

  1 208 3.8 Verilog

  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

• hdl_checker

  4 182 0.0 Python

  Repurposing existing HDL tools to help writing better code

• open-register-design-tool

  2 181 5.3 Verilog

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• veridian

  3 104 4.8 Rust

  A SystemVerilog Language Server

Project mention: How to configure vim like an IDE | /r/vim | 2023-06-27

SystemVerilog

• cheshire

  1 102 7.8 SystemVerilog

  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  

Project mention: Cpu project | /r/RISCV | 2023-05-08

If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here

• BrianHG-DDR3-Controller

  2 60 10.0 SystemVerilog

  DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

• deepsocflow

  1 34 9.1 Python

  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

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Systemverilog related posts

• Veryl: A Modern Hardware Description Language
  3 projects | news.ycombinator.com | 12 Mar 2024
• How to instance module with auto-completion for verilog in neovim?
  1 project | /r/neovim | 25 Aug 2023
• Verilog functions and wires
  1 project | /r/Verilog | 11 Jun 2023
• How to design a more elegant and simple instraction decoder
  1 project | /r/RISCV | 24 May 2023
• An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
  5 projects | /r/ProgrammingLanguages | 3 May 2023
• Sigasi's price
  1 project | /r/FPGA | 6 Apr 2023
• How to keep files in memory in tower_lsp?
  1 project | /r/rust | 27 Feb 2023
• A note from our sponsor - SaaSHub
  www.saashub.com | 25 Apr 2024

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